257 search results - page 5 / 52 » An optimal algorithm for area minimization of slicing floorp... |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
In this paper, we present an integrated approach to floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus speci...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design ...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— In this paper, we introduce a novel substrate noise estimation technique during early floorplanning, based on the concept of Block Preference Directed Graph (BPDG) and the cla...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...