117 search results - page 13 / 24 » An optimal algorithm for sizing sequential circuits for indu... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Models of simulation program with integrated circuit emphasis (SPICE) are currently playing a central role in the connection between circuit design and chip fabrication communitie...
DAC
2003
ACM
14 years 22 days ago
2003
ACM
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
GECCO
2003
Springer
14 years 21 days ago
2003
Springer
Abstract. In this paper, we propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local op...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...