3120 search results - page 18 / 624 » An optimal architecture for a DDC |
APCSAC
2004
IEEE
14 years 3 days ago
2004
IEEE
Dynamic optimization presents opportunities for finding run-time bottlenecks and deploying optimizations in statically compiled programs. In this paper, we discuss our current impl...
DAC
1994
ACM
14 years 13 days ago
1994
ACM
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...
FCCM
2004
IEEE
14 years 2 days ago
2004
IEEE
ended abstract presents further results from the word-length optimization system Right-Size described at FCCM 2003. The system is used to quantify the compiletime specialization s...
ARVLSI
1995
IEEE
13 years 12 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
GECCO
2006
Springer
14 years 10 hour ago
2006
Springer
Achieving a high quality and cost-effective tests is a major concern for software buyers and sellers. Using tools and integrating techniques to carry out low cost testing are chal...