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DAC
2005
ACM
14 years 8 months ago
Multilevel full-chip routing for the X-based architecture
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-J...
IEEESCC
2010
IEEE
13 years 11 months ago
Towards Green Business Process Management
—There is a global consensus on the need to reduce our collective carbon footprint. While much research attention has focused on developing alternative energy sources, automotive...
Konstantin Hoesch-Klohe, Aditya Ghose, Lam-Son Le
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
14 years 2 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
MM
2006
ACM
203views Multimedia» more  MM 2006»
14 years 1 months ago
Learning image manifolds by semantic subspace projection
In many image retrieval applications, the mapping between highlevel semantic concept and low-level features is obtained through a learning process. Traditional approaches often as...
Jie Yu, Qi Tian
TVLSI
2008
139views more  TVLSI 2008»
13 years 7 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood