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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
GECCO
2007
Springer
156views Optimization» more  GECCO 2007»
14 years 1 months ago
Nonlinearity linkage detection for financial time series analysis
Standard detection algorithms for nonlinearity linkage fail when applied to typical problems in the analysis of financial time-series data. We explain how this failure arises whe...
Theodore Chiotis, Christopher D. Clack
IPSN
2010
Springer
14 years 2 months ago
Diagnostic powertracing for sensor node failure analysis
Troubleshooting unresponsive sensor nodes is a significant challenge in remote sensor network deployments. This paper introduces the tele-diagnostic powertracer, an in-situ troub...
Mohammad Maifi Hasan Khan, Hieu Khac Le, Michael L...
RTSS
2007
IEEE
14 years 1 months ago
Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms
In the last years, a progressive migration from single processor chips to multi-core computing devices has taken place in the general-purpose and embedded system market. The devel...
Marko Bertogna, Michele Cirinei
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
14 years 1 months ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...