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CODES
2006
IEEE
14 years 4 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
CODES
2007
IEEE
14 years 4 months ago
Probabilistic performance risk analysis at system-level
We present a novel hybrid approach for performance analysis of a system design. Unlike other approaches in this area, in this paper we do not focus on the determination of pessimi...
Alexander Viehl, Markus Schwarz, Oliver Bringmann,...
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
14 years 4 months ago
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
Mingjing Chen, Alex Orailoglu
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 10 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
DAC
2008
ACM
14 years 11 months ago
Functional test selection based on unsupervised support vector analysis
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Fo...