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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
PTS
2000
108views Hardware» more  PTS 2000»
13 years 8 months ago
Determination of Test Configurations for Pair-Wise Interaction Coverage
Systems constructed from components, including distributed systems, consist of a number of elements that interact with each other. As the number of network elements or interchangea...
Alan W. Williams
DATE
2004
IEEE
156views Hardware» more  DATE 2004»
13 years 10 months ago
Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches
In this paper, we propose an approach to estimate the Worst Case Response Time (WCRT) of tasks in a preemptive multi-tasking single-processor real-time system with a set associati...
Yudong Tan, Vincent John Mooney III
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 10 days ago
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chak...
EDBT
2008
ACM
135views Database» more  EDBT 2008»
14 years 6 months ago
Minimizing latency and memory in DSMS: a unified approach to quasi-optimal scheduling
Data Stream Management Systems (DSMSs) must support optimized execution scheduling of multiple continuous queries on massive, and frequently bursty, data streams. Previous approac...
Yijian Bai, Carlo Zaniolo