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» Analysis and Optimization of CHR Programs
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IEEEPACT
2008
IEEE
14 years 4 months ago
Exploiting loop-dependent stream reuse for stream processors
The memory access limits the performance of stream processors. By exploiting the reuse of data held in the Stream Register File (SRF), an on-chip storage, the number of memory acc...
Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers,...
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
14 years 4 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
CASES
2003
ACM
14 years 3 months ago
Polynomial-time algorithm for on-chip scratchpad memory partitioning
Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main ...
Federico Angiolini, Luca Benini, Alberto Caprara
FPL
2007
Springer
99views Hardware» more  FPL 2007»
14 years 2 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
AAAI
2007
14 years 21 days ago
Nonmyopic Informative Path Planning in Spatio-Temporal Models
In many sensing applications we must continuously gather information to provide a good estimate of the state of the environment at every point in time. A robot may tour an environ...
Alexandra Meliou, Andreas Krause, Carlos Guestrin,...