115 search results - page 14 / 23 » Analysis and optimization of gate leakage current of power g... |
DAC
2004
ACM
13 years 11 months ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
CHES
2005
Springer
14 years 1 months ago
2005
Springer
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate...
SLIP
2009
ACM
14 years 2 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
IPCCC
2007
IEEE
14 years 2 months ago
2007
IEEE
Leakage power is a major concern in current microarchitectures as it is increasing exponentially with decreasing transistor feature sizes. In this paper, we present a technique ca...
CHES
2006
Springer
13 years 11 months ago
2006
Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...