In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfg...