562 search results - page 81 / 113 » Analysis of Hardware Acceleration in Reconfigurable Embedded... |
DATE
2008
IEEE
13 years 9 months ago
2008
IEEE
In this paper, we propose a simulation-based methodology for worst-case response time estimation of distributed realtime systems. Schedulability analysis produces pessimistic uppe...
FPL
2010
Springer
13 years 5 months ago
2010
Springer
Abstract--Modular multiplication of long integers is an important building block for cryptographic algorithms. Although several FPGA accelerators have been proposed for large modul...
WORDS
2002
IEEE
14 years 19 days ago
2002
IEEE
The Worst-Case Execution-Time Analysis (WCET Analysis) of program code that is to be executed on modern processors is a highly complex task. First, it involves path analysis, to i...
DASIP
2010
13 years 2 months ago
2010
Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++...
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...