562 search results - page 86 / 113 » Analysis of Hardware Acceleration in Reconfigurable Embedded... |
MEMOCODE
2003
IEEE
14 years 1 months ago
2003
IEEE
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
RTCSA
2009
IEEE
14 years 2 months ago
2009
IEEE
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
ERSA
2008
13 years 9 months ago
2008
Projected computational requirements for future space missions are outpacing technologies and trends in conventional embedded microprocessors. In order to meet the necessary levels...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...