120 search results - page 20 / 24 » Analysis of Memory Hierarchy Performance of Block Data Layou... |
OOPSLA
2004
Springer
14 years 27 days ago
2004
Springer
As improvements in processor speed continue to outpace improvements in cache and memory speed, poor locality increasingly degrades performance. Because copying garbage collectors ...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
SIPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...
ICS
2009
Tsinghua U.
13 years 5 months ago
2009
Tsinghua U.
In the search for high performance, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. The TM system must then...
RTAS
1996
IEEE
13 years 11 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...