32 search results - page 4 / 7 » Analysis of SEU Effects in a Pipelined Processor |
ISCA
2003
IEEE
14 years 22 days ago
2003
IEEE
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
VEE
2012
ACM
12 years 3 months ago
2012
ACM
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
PDPTA
2003
13 years 8 months ago
2003
This paper presents the effectiveness of an interactive support facility to tune processor allocation of data-driven realtime programs on CUE (Coordinating Users’ requirements an...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Pipeline flushes due to branch mispredictions is one of the most serious problems facing the designer of a deeply pipelined, superscalar processor. Many branch predictors have bee...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...