291 search results - page 15 / 59 » Analysis of a reconfigurable network processor |
IPPS
1999
IEEE
14 years 1 months ago
1999
IEEE
HeteroSort load balances and sorts within static or dynamic networks. Upon failure of a node or path, HeteroSort uses a genetic algorithm to minimize the distribution path by optim...
ERSA
2006
13 years 10 months ago
2006
- An intrinsic embedded online evolution system has been designed using Block-based neural networks and implemented on Xilinx VirtexIIPro FPGAs. The designed network can dynamicall...
SUTC
2008
IEEE
14 years 3 months ago
2008
IEEE
As the robotic industry is growing boomingly, the functionalities and system's architecture of robots are more and more complex. The development of robotic application system...
ISCA
2000
IEEE
14 years 17 days ago
2000
IEEE
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...