65 search results - page 2 / 13 » Analysis of buffered hybrid structured clock networks |
TVLSI
2010
13 years 2 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
ICW
2005
IEEE
14 years 1 months ago
2005
IEEE
A QoS provisioned CIOQ switch using crossbar structure with m parallel lines per output port is proposed in this paper. The packets at input buffers are transferred to the output ...
TON
1998
13 years 7 months ago
1998
This paper describes the analysis, implementation and performance of a new algorithm engineered to discipline a computer clock to a source of standard time, such as a GPS receiver...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...