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» Analysis of communication delay bounds for network on chips
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IESS
2007
Springer
165views Hardware» more  IESS 2007»
14 years 3 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
ANCS
2007
ACM
14 years 1 months ago
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
CONEXT
2005
ACM
13 years 11 months ago
Real-time communication over switched ethernet for military applications
Full-Duplex Switched Ethernet is a forecasted new technology for advanced military aircraft system interconnection. However, it was not originally developed to meet the requiremen...
Ahlem Mifdaoui, Fabrice Frances, Christian Fraboul
PIMRC
2010
IEEE
13 years 6 months ago
Frame delay distribution analysis of IEEE 802.11 networks using Signal Flow Graphs
Frame delay variance in CSMA/CA networks is large. Wireless applications may require both, limited mean delay and limited delay jitter. These parameters can be derived easily from ...
Ralf Jennen, Sebastian Max, Bernhard Walke
MASCOTS
2007
13 years 10 months ago
Distance Reduction in Mobile Wireless Communication: Lower Bound Analysis and Practical Attainment
— The transmission energy required for a wireless communication increases superlinearly with the communication distance. In a mobile wireless network, nodal movement can be explo...
Yu Dong, Wing-Kai Hon, David K. Y. Yau, Jren-Chit ...