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» Analysis of power consumption in memory hierarchies
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ICMCS
2006
IEEE
141views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Scalability of Multimedia Applications on Next-Generation Processors
In the near future, the majority of personal computers are expected to have several processing units. This is referred to as Core Multiprocessing (CMP). Furthermore, each of the c...
Guy Amit, Yaron Caspi, Ran Vitale, Adi Pinhas
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 23 days ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
TJS
2002
121views more  TJS 2002»
13 years 7 months ago
Precise Data Locality Optimization of Nested Loops
A significant source for enhancing application performance and for reducing power consumption in embedded processor applications is to improve the usage of the memory hierarchy. In...
Vincent Loechner, Benoît Meister, Philippe C...
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
13 years 11 months ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili
BTW
2009
Springer
146views Database» more  BTW 2009»
14 years 2 months ago
Towards Flash Disk Use in Databases - Keeping Performance While Saving Energy?
Abstract: Green computing or energy saving when processing information is primarily considered a task of processor development. We, however, advocate that a holistic approach is ne...
Theo Härder, Karsten Schmidt 0002, Yi Ou, Seb...