99 search results - page 3 / 20 » Analysis of power consumption in memory hierarchies |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
VLSISP
2008
13 years 7 months ago
2008
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...
DATE
2003
IEEE
14 years 24 days ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...