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DOCENG
2007
ACM
13 years 11 months ago
Speculative document evaluation
Optimisation of real world Variable Data printing (VDP) documents is a difficult problem because the interdependencies between layout functions may drastically reduce the number o...
Alexander J. Macdonald, David F. Brailsford, Steve...
HPCA
2008
IEEE
14 years 8 months ago
Runahead Threads to improve SMT performance
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
Tanausú Ramírez, Alex Pajuelo, Olive...
HPCA
2005
IEEE
14 years 1 months ago
Chip Multithreading: Opportunities and Challenges
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...
Lawrence Spracklen, Santosh G. Abraham
TC
1998
13 years 7 months ago
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...
Fredrik Dahlgren, Michel Dubois, Per Stenströ...
MICRO
2000
IEEE
98views Hardware» more  MICRO 2000»
13 years 12 months ago
The store-load address table and speculative register promotion
Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot alw...
Matt Postiff, David Greene, Trevor N. Mudge