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ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
14 years 4 months ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha
ISPASS
2009
IEEE
14 years 2 months ago
The data-centricity of Web 2.0 workloads and its impact on server performance
Advances in network performance and browser technologies, coupled with the ubiquity of internet access and proliferation of users, have lead to the emergence of a new class of web...
Moriyoshi Ohara, Priya Nagpurkar, Yohei Ueda, Kazu...
ISPASS
2009
IEEE
14 years 2 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
14 years 2 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
GECCO
2009
Springer
142views Optimization» more  GECCO 2009»
14 years 1 months ago
A stopping criterion based on Kalman estimation techniques with several progress indicators
The need for a stopping criterion in MOEA’s is a repeatedly mentioned matter in the domain of MOOP’s, even though it is usually left aside as secondary, while stopping criteri...
José Luis Guerrero, Jesús Garc&iacut...