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» Application mapping for chip multiprocessors
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CODES
2006
IEEE
15 years 10 months ago
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs (intellectual property) alo...
Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nali...
ICCCN
2007
IEEE
15 years 10 months ago
Lagniappe: Multi-* Programming Made Simple
—The emergence of multi-processor, multi-threaded architectures (referred to as multi- architectures) facilitates the design of high-throughput request processing systems (e.g., ...
Taylor L. Riché, R. Greg Lavender, Harrick ...
IEEEPACT
2007
IEEE
15 years 10 months ago
Speculative Decoupled Software Pipelining
In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-core processors. To avoid burdening programmers with the responsibility of paralle...
Neil Vachharajani, Ram Rangan, Easwaran Raman, Mat...
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
15 years 10 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
15 years 7 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad