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» Application of Reduce Order Modeling to Time Parallelization
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DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
LCTRTS
2010
Springer
14 years 2 months ago
Sampling-based program execution monitoring
For its high overall cost during product development, program debugging is an important aspect of system development. Debugging is a hard and complex activity, especially in time-...
Sebastian Fischmeister, Yanmeng Ba
GLOBECOM
2008
IEEE
14 years 2 months ago
Multi-Cluster Multi-Parent Wake-Up Scheduling in Delay-Sensitive Wireless Sensor Networks
—Immediate notification of urgent but rare events and delivery of time sensitive actuation commands appear in many practical wireless sensor and actuator network applications. M...
Huang Lee, Abtin Keshavarzian, Hamid K. Aghajan
CODES
2007
IEEE
14 years 2 months ago
HW/SW co-design for Esterel processing
We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The startin...
Sascha Gädtke, Claus Traulsen, Reinhard von H...
SAFECOMP
2005
Springer
14 years 1 months ago
Are High-Level Languages Suitable for Robust Telecoms Software?
In the telecommunications sector product development must minimise time to market while delivering high levels of dependability, availability, maintainability and scalability. High...
Jan Henry Nyström, Philip W. Trinder, David J...