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LCTRTS
2001
Springer
13 years 11 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 7 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 1 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
CODES
2005
IEEE
14 years 28 days ago
Conflict analysis in multiprocess synthesis for optimized system integration
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
Oliver Bringmann, Wolfgang Rosenstiel, Axel Sieben...
CP
2008
Springer
13 years 9 months ago
An Application of Constraint Programming to Superblock Instruction Scheduling
Modern computer architectures have complex features that can only be fully taken advantage of if the compiler schedules the compiled code. A standard region of code for scheduling ...
Abid M. Malik, Michael Chase, Tyrel Russell, Peter...