Sciweavers

86 search results - page 11 / 18
» Application-Specific Computing with Adaptive Register File A...
Sort
View
HPCA
2006
IEEE
14 years 7 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
CF
2009
ACM
14 years 2 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
CLUSTER
2002
IEEE
13 years 7 months ago
ZENTURIO: An Experiment Management System for Cluster and Grid Computing
The need to conduct and manage large sets of experiments for scientific applications dramatically increased over the last decade. However, there is still very little tool support ...
Radu Prodan, Thomas Fahringer
DAC
2009
ACM
13 years 8 months ago
Way Stealing: cache-assisted automatic instruction set extensions
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
DAC
2006
ACM
14 years 8 months ago
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performanc...
Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra