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DAC
2005
ACM
13 years 10 months ago
Exploring technology alternatives for nano-scale FPGA interconnects
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the ...
Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane I...
CORR
2008
Springer
77views Education» more  CORR 2008»
13 years 8 months ago
A Reconfigurable Impedance Matching Network Employing RF-MEMS Switches
We propose the design of a reconfigurable impedance matching network for the lower RF frequency band, based on a developed RF-MEMS technology. The circuit is composed of RF-MEMS o...
Marco Bedani, F. Carozza, Roberto Gaddi, Antonio G...
DAM
2006
120views more  DAM 2006»
13 years 8 months ago
A bijection between permutations and floorplans, and its applications
A floorplan represents the relative relations between modules on an integrated circuit. Floorplans are commonly classified as slicing, mosaic, or general. Separable and Baxter per...
Eyal Ackerman, Gill Barequet, Ron Y. Pinter
DAC
2011
ACM
12 years 8 months ago
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
Jason Cong, Guojie Luo, Yiyu Shi
DAC
2011
ACM
12 years 8 months ago
Fault-tolerant 3D clock network
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...