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FDL
2003
IEEE
14 years 1 months ago
Using Symbolic Simulation for Bounded Property Checking
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
Jürgen Ruf, Prakash Mohan Peranandam, Thomas ...
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
14 years 1 months ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
IPPS
2003
IEEE
14 years 1 months ago
Parallel Tabu Search in a Heterogeneous Environment
In this paper, we discuss a parallel tabu search algorithm with implementation in a heterogeneous environment. Two parallelization strategies are integrated: functional decomposit...
Ahmad A. Al-Yamani, Sadiq M. Sait, Hassan Barada, ...
ISCAS
2003
IEEE
119views Hardware» more  ISCAS 2003»
14 years 1 months ago
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning
In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective versio...
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji