—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
In this paper, an adaptive sampling method is proposed for the statistical SRAM cell analysis. The method is composed of two components. One part is the adaptive sampler that manip...
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...