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ISPD
2003
ACM
151views Hardware» more  ISPD 2003»
14 years 1 months ago
Capturing crosstalk-induced waveform for accurate static timing analysis
We propose a method to capture crosstalk-induced noisy waveform for crosstalk-aware static timing analysis. The effects of capacitive coupling noise on timing are conventionally m...
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 25 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
VLSID
2002
IEEE
100views VLSI» more  VLSID 2002»
14 years 24 days ago
Layout-Driven Timing Optimization by Generalized De Morgan Transform
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
Supratik Chakraborty, Rajeev Murgai
DAC
2010
ACM
13 years 11 months ago
Cost-aware three-dimensional (3D) many-core multiprocessor design
The emerging three-dimensional integrated circuit (3D IC) is beneficial for various applications from both area and performance perspectives. While the general trend in processor...
Jishen Zhao, Xiangyu Dong, Yuan Xie
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
13 years 11 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...