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ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 8 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
DSD
2010
IEEE
99views Hardware» more  DSD 2010»
13 years 8 months ago
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies
—Several alternatives of mesh-type topologies have been published for the use in Networks-on-Chip. Due to their regularity, mesh-type topologies often serve as a foundation to in...
Claas Cornelius, Philipp Gorski, Stephan Kubisch, ...
GLVLSI
2010
IEEE
168views VLSI» more  GLVLSI 2010»
13 years 8 months ago
A revisit to voltage partitioning problem
We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E = CV 2 , a published wo...
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi G...
CODES
2008
IEEE
13 years 8 months ago
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
CSUR
2006
147views more  CSUR 2006»
13 years 7 months ago
A survey of research and practices of Network-on-chip
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
Tobias Bjerregaard, Shankar Mahadevan