This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
- Bundled multi-walled carbon nanotubes (MWNT) were successfully and repeatably manipulated by AC electrophoresis to form resistive elements between Au microelectrodes and were dem...
Bulk multi-walled carbon nanotube (MWNT) were successfully and repeatably manipulated by AC electrophoresis to form resistive elements between Au microelectrodes and were demonstr...
— We discuss a fault diagnosis scheme for analog integrated circuits. Our approach is based on an assemblage of learning machines that are trained beforehand to guide us through ...
Ke Huang, Haralampos-G. D. Stratigopoulos, Salvado...
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...