259 search results - page 24 / 52 » Application-specific instruction generation for configurable... |
MICRO
2003
IEEE
14 years 20 days ago
2003
IEEE
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Langua...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...