This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objec...
Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonock...
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
Abstract—Developers introduce novel and undocumented micro-architectures when performing evolution tasks on object-oriented applications. We are interested in understanding wheth...
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...