59 search results - page 4 / 12 » Applying Formal Methods for Human Error Tolerant Design |
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
COMPSAC
2007
IEEE
14 years 1 months ago
2007
IEEE
Building open distributed systems is an even more challenging task than building distributed systems, as their components are loosely synchronised, can move, become disconnected, ...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
IUI
2006
ACM
14 years 1 months ago
2006
ACM
Spoken dialog tasks incur many errors including speech recognition errors, understanding errors, and even dialog management errors. These errors create a big gap between user'...