62 search results - page 4 / 13 » Applying Logic Synthesis for Speeding Up SAT |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
As we move towards nanometer technology, manufacturing problems become overwhelmingly difficult to solve. Presently, optimization for manufacturability is performed at a post-synt...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
TACAS
2010
Springer
14 years 2 months ago
2010
Springer
Boolean satisfiability (SAT) and its extensions are becoming a core technology for the analysis of systems. The SAT-based approach divides into three steps: encoding, preprocessin...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...