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» Approximation Approach for Timing Jitter Characterization in...
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ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 7 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 11 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
13 years 11 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
MICCAI
2006
Springer
14 years 8 months ago
Anatomical Modelling of the Musculoskeletal System from MRI
Abstract. This paper presents a novel approach for multi-organ (musculoskeletal system) automatic registration and segmentation from clinical MRI datasets, based on discrete deform...
Benjamin Gilles, Laurent Moccozet, Nadia Magnenat-...