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CASES
2008
ACM
13 years 9 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
DATE
2006
IEEE
171views Hardware» more  DATE 2006»
14 years 1 months ago
4G applications, architectures, design methodology and tools for MPSoC
transistors the design of the SoC needs to be moved to a higher level of abstraction. We need to think in processors and interconnects rather than gates and wires. We discuss the n...
BIRTHDAY
1991
Springer
13 years 11 months ago
User Interface Development: Problems and Experiences
: In this paper, we present a software engineer's view of user-interface development. First, we illustrate the main problem areas responsible for difficulties in building high...
Hans-Werner Six, Josef Voss
ERSA
2006
133views Hardware» more  ERSA 2006»
13 years 9 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan