412 search results - page 16 / 83 » Architectural Considerations for Energy Efficiency |
ECCTD
2011
12 years 8 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...
DATE
2004
IEEE
14 years 5 days ago
2004
IEEE
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
SIGMOD
2010
ACM
13 years 8 months ago
2010
ACM
Rising energy costs in large data centers are driving an agenda for energy-efficient computing. In this paper, we focus on the role of database software in affecting, and, ultimat...
PDP
2010
IEEE
14 years 22 days ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
TCAD
2002
13 years 8 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...