412 search results - page 70 / 83 » Architectural Considerations for Energy Efficiency |
CODES
2010
IEEE
13 years 6 months ago
2010
IEEE
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
ICIP
2006
IEEE
14 years 10 months ago
2006
IEEE
In this paper we propose a new framework for modeling 2D shapes. A shape is first described by a sequence of local features (e.g., curvature) of the shape boundary. The resulting ...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
A motion adaptive de-interlacing algorithm and its hardware architecture are presented in this paper. It consists the directional interpolation - ELA with median processing, and 4...