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CODES
2000
IEEE
14 years 12 days ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf
WMPI
2004
ACM
14 years 1 months ago
Compiler-optimized usage of partitioned memories
In order to meet the requirements concerning both performance and energy consumption in embedded systems, new memory architectures are being introduced. Beside the well-known use o...
Lars Wehmeyer, Urs Helmig, Peter Marwedel
ISSS
1996
IEEE
134views Hardware» more  ISSS 1996»
14 years 4 days ago
ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures
An address generation and optimization environment (ADOPT) for distributed memory architectures, is presented. ADOPT is oriented to minimize the area overhead introduced by the us...
Miguel Miranda, Francky Catthoor, Martin Janssen, ...
CODES
2007
IEEE
14 years 2 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
RSP
2003
IEEE
147views Control Systems» more  RSP 2003»
14 years 1 months ago
Cache Configuration Exploration on Prototyping Platforms
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
Chuanjun Zhang, Frank Vahid