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ISCA
2008
IEEE
136views Hardware» more  ISCA 2008»
13 years 7 months ago
The Design and Performance of a Bare PC Web Server
There is an increasing need for new Web server architectures that are application-centric, simple, small, and pervasive in nature. In this paper, we present a novel architecture f...
Long He, Ramesh K. Karne, Alexander L. Wijesinha
ARC
2009
Springer
165views Hardware» more  ARC 2009»
14 years 1 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 9 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
RTSS
2003
IEEE
14 years 10 days ago
Data Caches in Multitasking Hard Real-Time Systems
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
Xavier Vera, Björn Lisper, Jingling Xue
CEC
2010
IEEE
13 years 8 months ago
An adaptive ensemble of fuzzy ARTMAP neural networks for video-based face classification
A key feature in population based optimization algorithms is the ability to explore a search space and make a decision based on multiple solutions. In this paper, an incremental le...
Jean-François Connolly, Eric Granger, Rober...