36 search results - page 7 / 8 » Architectural Power Optimization by Bus Splitting |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
IROS
2007
IEEE
14 years 1 months ago
2007
IEEE
— We present a refined, second-generation design, construction and integration, of a compact hyper-redundant snakelike robot, called “Woodstock.” This robot has substantial a...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...