77 search results - page 4 / 16 » Architectural Support for Runtime 2D Partial Reconfiguration |
ERSA
2009
13 years 5 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
FCCM
1997
IEEE
13 years 12 months ago
1997
IEEE
By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we descri...
FCCM
2009
IEEE
14 years 2 months ago
2009
IEEE
—Wireless sensor networks (WSNs) are typically composed of very small, battery-operated devices (sensor nodes) containing simple microprocessors with few computational resources....
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
ERSA
2003
13 years 9 months ago
2003
Many embedded applications can benefit from the flexible custom computing opportunities that FPGA technology offers. The Run-Time Reconfiguration (RTR) of the FPGA as an applicati...