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» Architectural Synthesis of Timed Asynchronous Systems
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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
EMSOFT
2004
Springer
14 years 2 months ago
Heterogeneous reactive systems modeling: capturing causality and the correctness of loosely time-triggered architectures (LTTA)
We present an extension of a mathematical framework proposed by the authors to deal with the composition of heterogeneous reactive systems. Our extended framework encompasses dive...
Albert Benveniste, Benoît Caillaud, Luca P. ...
EUROMICRO
1999
IEEE
14 years 28 days ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
DAC
2009
ACM
14 years 9 months ago
Quality-driven synthesis of embedded multi-mode control systems
At runtime, an embedded control system can switch between alternative functional modes. In each mode, the system operates by using a schedule and controllers that exploit the avai...
Soheil Samii, Petru Eles, Zebo Peng, Anton Cervin
ICCAD
2002
IEEE
103views Hardware» more  ICCAD 2002»
14 years 5 months ago
Synthesis of customized loop caches for core-based embedded systems
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
Susan Cotterell, Frank Vahid