Sciweavers

67 search results - page 1 / 14
» Architectural analysis and instruction-set optimization for ...
Sort
View
DAC
2009
ACM
14 years 8 months ago
Way Stealing:cache-assisted automatic instruction set extensions
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
VLSID
2006
IEEE
142views VLSI» more  VLSID 2006»
14 years 7 months ago
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors
- Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, ...
Nachiketh R. Potlapally, Srivaths Ravi, Anand Ragh...
TVLSI
2008
187views more  TVLSI 2008»
13 years 7 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
CSREAESA
2006
13 years 8 months ago
Power Optimization of Interconnection Networks for Transport Triggered Architecture
Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of...
Xue-mi Zhao, Zhiying Wang