312 search results - page 4 / 63 » Architectural approaches to reduce leakage energy in caches |
ICCD
2008
IEEE
14 years 7 months ago
2008
IEEE
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...
DATE
2004
IEEE
14 years 2 months ago
2004
IEEE
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
ASPDAC
2006
ACM
14 years 4 months ago
2006
ACM
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...
MICRO
2005
IEEE
14 years 4 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
ICCD
2006
IEEE
14 years 7 months ago
2006
IEEE
— L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access...