268 search results - page 15 / 54 » Architectural descriptions for FPGA circuits |
FPL
2009
Springer
14 years 1 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
FPGA
2011
ACM
13 years 5 days ago
2011
ACM
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
FPGA
2000
ACM
14 years 8 days ago
2000
ACM
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
TCAD
2010
13 years 3 months ago
2010
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...