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» Architectural descriptions for FPGA circuits
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DAC
2002
ACM
14 years 9 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
FCCM
2005
IEEE
131views VLSI» more  FCCM 2005»
14 years 2 months ago
Automating the Layout of Reconfigurable Subsystems Using Circuit Generators
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
Shawn Phillips, Scott Hauck
DAC
2005
ACM
14 years 9 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
DAC
2006
ACM
14 years 9 months ago
FLAW: FPGA lifetime awareness
Aggressive scaling of technology has an adverse impact on the reliability of VLSI circuits. Apart from increasing transient error susceptibility, the circuits also become more vul...
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie,...
FPL
2006
Springer
211views Hardware» more  FPL 2006»
14 years 11 days ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...