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» Architectural descriptions for FPGA circuits
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GLVLSI
2009
IEEE
154views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
Yanjie Peng, Andrew G. Klein, Xinming Huang
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
14 years 1 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
FPL
2000
Springer
128views Hardware» more  FPL 2000»
13 years 11 months ago
Verification of Dynamically Reconfigurable Logic
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
David Robinson, Patrick Lysaght
MEMOCODE
2010
IEEE
13 years 5 months ago
A regular expression matching using non-deterministic finite automaton
Abstract--This paper shows an implementation of CANSCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the pa...
Hiroshi Nakahara, Tsutomu Sasao, Munehiro Matsuura
DAC
2004
ACM
14 years 8 months ago
Automated fixed-point data-type optimization tool for signal processing and communication systems
A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point d...
Changchun Shi, Robert W. Brodersen