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ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
14 years 2 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
WWW
2005
ACM
14 years 9 months ago
Web services security configuration in a service-oriented architecture
Security is one of the major concerns when developing missioncritical business applications, and this concern motivated the Web Services Security specifications. However, the exis...
Takeshi Imamura, Michiaki Tatsubori, Yuichi Nakamu...
GI
2001
Springer
14 years 1 months ago
Towards a Novel Architecture to Support Universal Location Awareness
—The rapid advances in a wide range of wireless access technologies along with an industry-wide IP-convergence have set up the stage for context-aware computing. The “locationâ...
Amiya Bhattacharya, Abhishek Roy, Sajal K. Das
CASES
2007
ACM
14 years 27 days ago
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local...
Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo K...
ICASSP
2010
IEEE
13 years 6 months ago
Bandwidth-intensive FPGA architecture for multi-dimensional DFT
Multi-dimensional (MD) Discrete Fourier Transform (DFT) is a key kernel algorithm in many signal processing algorithms, including radar data processing and medical imaging. Althou...
Chi-Li Yu, Chaitali Chakrabarti, Sungho Park, Vija...